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cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v 8 k/16 k/32 k/64 k 18 low voltage deep sync fifos cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-06012 rev. *d revised december 31, 2010 32 k/64 k 18 low voltage deep sync fifos features 3.3 v operation for low power consumption and easy integration into low voltage systems high speed, low power, first-in first-out (fifo) memories 8 k 18 (cy7c4255v) 16 k 18 (cy7c4265v) 32 k 18 (cy7c4275v) 64 k 18 (cy7c4285v) 0.35 micron cmos for optimum speed and power high speed 100 mhz ope ration (10 ns read/write cycle times) low power ? i cc = 30 ma ? i sb = 4 ma fully asynchronous and simultaneous read and write operation empty, full, half full, and programmable almost empty and almost full status flags retransmit function output enable (oe ) pin independent read and write enable pins supports free running 50% duty cycle clock inputs width expansion capability depth expansion capability 64-pin 1010 stqfp pin compatible density upgrade to cy7c42x5v-asc families pin compatible 3.3 v solutions for cy7c4255/65/75/85v functional description the cy7c4255/65/75/85v are high speed, low power, first-in first-out (fifo) memories with cl ocked read and write interfaces. all are 18 bits wide and are pin and functionally compatible to the cy7c42x5v synchronous fifo family. the cy7c4255/65/75/85v can be cascaded to increase fifo depth. programmable features include almost full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering. these fifos have 18-bit input and output ports that are controlled by separate clock and enable signals. the input port is controlled by a free-running clock (wclk) and a write enable pin (wen). when wen is asserted, data is written into the fifo on the rising edge of the wclk signal. while wen is held active, data is continually written into the fi fo on each cycle. the output port is controlled in a similar manner by a free-running read clock (rclk) and a read enable pin (ren). in addition, the cy7c4255/65/75/85v have an outp ut enable pin (oe). the read and write clocks may be tied toge ther for single-clock operation or the two clocks may be run independently for asynchronous read or write applications. clock frequencies up to 67 mhz are achievable. retransmit and synchronous almost full/almost empty flag features are available on these devices. depth expansion is possible usin g the cascade input (wxi, rxi), cascade output (wxo, rxo), and first load (fl) pins. the wxo and rxo pins are connected to the wxi and rxi pins of the next device, and the wxo an d rxo pins of the last device must be connected to the wxi and rxi pins of the first device. the fl pin of the first device is tied to vss and the fl pin of all the remaining devices mu st be tied to vcc . selection guide parameter 7c4255/65/75/85v-10 7c4255/65/75/85v-15 maximum frequency (mhz) 100 66.7 maximum access time (ns) 8 10 minimum cycle time (ns) 10 15 minimum data or enable setup (ns) 3.5 4 minimum data or enable hold (ns) 0 0 maximum flag delay (ns) 8 10 active power su pply current (i cc1 ) (ma) commercial 30 30 industrial 35 [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 2 of 24 parameter cy7c4255v cy7c4265v cy7c4275v cy7c4285v density 8 k 18 16 k 18 32 k 18 64 k 18 package 64-pin 1010 tqfp 64-pin 1010 tq fp 64-pin 1010 tqfp 64-pin 1010 tqfp logic block diagram q 0? 17 4275v?1 three-st ate output register read control flag logic write control write pointer read pointer reset logic expansion logic input register flag program register d 0? 17 ren rclk ff ef pae wen wclk rs fl /rt wxi oe paf wxo /hf rxi rxo smode high density dual-port ram array 8kx9 32kx9 16kx9 64kx9 [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 3 of 24 contents pinouts .............................................................................. 4 functional description ..................................................... 6 architecture ...................................................................... 6 resetting the fifo ............................................................ 6 fifo operation ................................................................. 6 programming .................................................................... 6 flag operation .................................................................. 6 full flag ....................................................................... 6 empty flag .................................................................. 6 programmable almost empty/ almost full flag ........... 7 retransmit ......................................................................... 7 width expansion configuration ...................................... 7 depth expansion configuration (with programmable flags) ............................................. 8 maximum ratings ........................................................... 10 operating range ............................................................. 10 electrical characteristics ............................................... 10 capacitance .................................................................... 10 switching characteristics .............................................. 12 switching waveforms .................................................... 13 ordering information ...................................................... 21 ordering code definitions ..... .................................... 21 package diagram ............................................................ 22 acronyms ........................................................................ 23 document conventions ................................................. 23 units of measure ....................................................... 23 document history page ................................................. 24 sales, solutions, and legal information ...................... 24 worldwide sales and design s upport ......... .............. 24 products .................................................................... 24 psoc solutions ......................................................... 24 [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 4 of 24 pinouts figure 1. pin diagram - 64-pin stqfp ef top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 16 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 15 q 15 gnd q 16 q 17 gnd v cc rs oe ld ren rclk gnd d 17 d 16 pae wclk wen wxi v cc paf rxi ff wxo /hf rxo q 0 q 1 gnd q 2 q 3 q 14 q 13 gnd q 12 q 11 v cc q 10 q 9 gnd q 8 q 7 q 6 q 5 gnd q 4 v cc v cc /smode fl /rt 4275v?3 cy7c4255v cy7c4265v cy7c4275v cy7c4285v [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 5 of 24 table 1. pin definitions - cy7c4255/65/75/85v 64-pin stqfp signal name description io function d 0?17 data inputs i data inputs for an 18-bit bus. q 0?17 data outputs o data outputs for an 18-bit bus. wen write enable i enables the wclk input. ren read enable i enables the rclk input. wclk write clock i the rising edge clocks data into the fifo when wen is low and the fifo is not full. when ld is asserted, wclk writes data into the programmable flag-offset register. rclk read clock i the rising edge clocks data out of the fifo when ren is low and the fifo is not empty. when ld is asserted, rclk reads data out of the programmable flag-offset register. wxo /hf write expansion out/half full flag o dual mode pin: single device or width expansion ? half full status flag cascaded ? write expansion out signal, connected to wxi of next device ef empty flag o when ef is low, the fifo is empty. ef is synchronized to rclk. ff full flag o when ff is low, the fifo is full. ff is synchronized to wclk. pae programmable almost empty o when pae is low, the fifo is almost empty based on the almost empty offset value programmed into the fifo. pae is asynchronous when v cc /smode is tied to v cc . it is synchronized to rclk when v cc /smode is tied to v ss . paf programmable almost full o when paf is low, the fifo is almost full based on the almost full offset value programmed into the fifo. paf is asynchronous when v cc /smode is tied to v cc . it is synchronized to wclk when v cc /smode is tied to v ss . ld load i when ld is low, d 0?17 (q 0?17 ) are written (read) into (from) the programmable-flag-of fset register. fl /rt first load/ retransmit i dual mode pin: cascaded ? the first device in the daisy chain has fl tied to v ss ; all other devices have fl tied to v cc . in standard mode or width expansion, fl is tied to v ss on all devices. not cascaded ? tied to v ss . retransmit function is also available in standalone mode by strobing rt. wxi write expansion input i cascaded ? connected to wxo of previous device not cascaded ? tied to v ss rxi read expansion input i cascaded ? connected to rxo of previous device not cascaded ? tied to v ss rxo read expansion output o cascaded ? connected to rxi of next device rs reset i resets device to empty condition. a reset is required before an initial read or write operation after power up. oe output enable i when oe is low, the fifo?s data outputs dr ive the bus to which they are connected. if oe is high, the fifo?s outputs ar e in high z (high-impedance) state. v cc /smode synchronous almost empty/ almost full flags i dual mode pin: asynchronous almost empty/almost full flags ? tied to v cc synchronous almost empty/almost full flags ? tied to v ss (almost empty synchronized to rclk, almost full synchronized to wclk.) [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 6 of 24 functional description the cy7c4255/65/75/85v provides five status pins. these pins are decoded to determine one of five states: empty, almost empty, half full, almost full, and full (see table 3 on page 7 ). the half full flag shares the wxo pin. this flag is valid in the standalone and width expansion configurations. in the depth expansion, this pin provides the expansion out (wxo ) information that is used to signal the next fifo when it is to be activated. the empty and full flags are synchronous, that is, they change state relative to either the read clock (rclk) or the write clock (wclk). when entering or exiting the empty states, the flag is updated exclusively by the rclk. the flag denoting full states is updated exclusively by wclk. the synchronous flag architecture guarantees that t he flags remain valid from one clock cycle to the ne xt. the almost empt y/almost full flags become synchronous if the v cc /smode is tied to v ss . all configurations are fabr icated using an advanced 0.35 ? cmos technology. input esd protection is greater than 2001 v, and latch-up is prevented by the use of guard rings. architecture the cy7c4255/65/75/85v consists of an array of 8k/16k/32k/64k words of 18 bits each (implemented by a dual port array of sram cells), a read pointer, a write pointer, control signals (rclk, wclk, ren , wen , rs ), and flags (ef , pae , hf , paf , ff ). the cy7c4255/65/75/85v al so includes the control signals wxi , rxi , wxo , rxo for depth expansion. resetting the fifo upon power up, the fifo must be reset with a reset (rs ) cycle. this causes the fifo to enter the empty condition signified by ef being low. all data outputs go low after the falling edge of rs only if oe is asserted. for the fifo to reset to its default state, the user must not read or write while rs is low. fifo operation when the wen signal is active (low), data present on the d 0?17 pins is written into the fifo on each rising edge of the wclk signal. similarly, when the ren signal is active low, data in the fifo memory is presented on the q 0?17 outputs. new data is presented on each rising edge of rclk while ren is active low and oe is low. ren must set up t ens before rclk for it to be a valid read function. wen must occur t ens before wclk for it to be a valid write function. an output enable (oe ) pin is provided to three-state the q 0?17 outputs when oe is deasserted. when oe is enabled (low), data in the output register is available to the q 0?17 outputs after t oe . if devices are cascaded, the oe function only outputs data on the fifo that is read enabled. the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and under flow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0?17 outputs even after additional reads occur. programming the cy7c4255/65/75/85v devices contain two 16-bit offset registers. data present on d 0?15 during a program write determine the distance from empty (full) that the almost empty (almost full) flags become active. if the user elects not to program the fifo?s flags, the defaul t offset values are used (see table 3 on page 7 ). when the load ld pin is set low and wen is set low, data on the inputs d 0?15 is written into the empty offset register on the first low-to-high transition of the write clock (wclk). when the ld pin and wen are held low then data is written into the full offset register on the second low-to-high transition of the write clock (wclk). the third transition of the write clock (wcl k) again writes to the empty offset register (see ta b l e 2 ). all offset registers do not have to be written at one time. one or two offset registers can be written and then, by bringing the ld pin high, the fifo is returned to normal read/write operation. when the ld pin is set low, and wen is low, the next offset register in sequence is written. the contents of the offset regi sters can be read on the output lines when the ld pin is set low and ren is set low. then, data can be read on the low- to-high transition of the read clock (rclk). flag operation the cy7c4255/65/75/85v devices provide five flag pins to indicate the condition of the fifo contents. empty and full are synchronous. pae and paf are synchronous if v cc /smode is tied to v ss . full flag the full flag (ff ) goes low when device is full. write operations are inhibited whenever ff is low regardless of the state of wen . ff is synchronized to wclk, that is, it is exclusively updated by each rising edge of wclk. empty flag the empty flag (ef ) goes low when the device is empty. read operations are inhibited whenever ef is low, regardless of the state of ren . ef is synchronized to rclk, that is, it is exclusively updated by each rising edge of rclk. table 2. write offset register ld wen wclk [1] selection 0 0 writing to offset registers: empty offset full offset 0 1 no operation 1 0 write into fifo 1 1 no operation note 1. the same selection sequence applies to reading from the registers. ren is enabled and read is performed on the low-to-high transition of rclk. [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 7 of 24 programmable almost empty/almost full flag the cy7c4255/65/75/85v features programmable almost empty and almost full flags. each flag can be programmed (described in section programming on page 6 ) a specific distance from the corresponding boundary flags (empty or full). when the fifo contains the number of words or fewer for which the flags have been programmed, the paf or pae is asserted, signifying that the fifo is eit her almost full or almost empty. see ta b l e 3 for a description of programmable flags. when the smode pin is tied low, the paf flag signal transition is caused by the rising edge of the write clock and the pae flag transition is caused by the rising edge of the read clock. retransmit the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. the retransmit (rt) input is active in the standalone and width expansion modes. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred and at least one word has been read since the last rs cycle. a high pulse on rt resets the internal read pointer to the first physical location of the fifo. wclk and rclk may be free running but must be disabled during and t rtr after the retransmit pulse. with every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. flags are governed by the relative locati ons of the read and write pointers and are updated during a retransmit cycle. data written to the fifo after activation of rt are transmitted also. the full depth of the fifo can be repeatedly retransmitted. width expansion configuration the cy7c4255/65/75/85v can be expanded in width to provide word widths greater than 18 in increments of 18. during width expansion mode, all control line inputs are common and all flags are available. empty (full) flags must be created by anding the empty (full) flags of every fifo. the pae and paf flags can be detected from any one device. this technique avoids reading data from, or writing data to the fifo that is ?staggered? by one clock cycle due to the variations in skew between rclk and wclk. figure 2 on page 8 demonstrates a 36-word width by using two cy7c4255/65/75/85vs. table 3. flag truth table number of words in fifo ff paf hf pae ef 7c4255v ? 8 k 18 7c4265v ? 16 k 18 7c4275v ? 32 k 18 7c4285v ? 64 k 18 0000 hhhll 1 to n [2] 1 to n [2] 1 to n [2] 1 to n [2] hhhlh (n+1) to 4096 (n+1) to 8192 (n+1) to 16384 (n+1) to 32768 h h h h h 4097 to (8192?(m+1)) 8193 to (16384 ?(m+1)) 16385 to (32768?(m+1)) 32769 to (65536 ?(m+1)) h h l h h (8192?m) [3] to 8192 (16384?m) [3] to 16384 (32768?m) [3] to 32767 (65536?m) [3] to 65535 hllhh 8192 16384 32768 65536 l l l h h notes 2. n = empty offset (default values: cy7c4255/65/75/85v n = 127). 3. m = full offset (default values: cy7c4255/65/75/85v n = 127). [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 8 of 24 depth expansion configurati on (with programmable flags) the cy7c4255/65/75/85v can easily be adapted to applications requiring more than 8 k/16 k/32 k/64 k words of buffering. figure 3 on page 9 shows depth expansion using three cy 7c4255/65/75/85vs. maximum depth is limited only by signal loading. follow these steps: 1. the first device must be designated by grounding the first load (fl ) control input. 2. all other device s must have fl in the high state. 3. the write expansion out (wxo ) pin of each device must be tied to the write expansion in (wxi ) pin of the next device. 4. the read expansion out (rxo ) pin of each device must be tied to the read expansion in (rxi ) pin of the next device. 5. all load (ld ) pins are tied together. 6. the half full flag (hf ) is not available in the d epth expansion configuration. 7. ef , ff , pae , and paf are created with composite flags by oring together these respective flags for monitoring. the composite pae and paf flags are not precise. figure 2. block diagram of 8 k/16 k/32 k/64 k 18 low voltag e synchronous fifo memory in width expansion configuration 4275v?24 ff ff ef ef write clock (wclk) write enable (wen ) load (ld ) programmable(pae ) half full flag (hf ) full flag (ff ) 7c4255v 7c4265v 18 36 data in (d) reset (rs) 18 reset (rs) read clock (rclk) read enable (ren ) output enable (oe ) programmable (paf ) empty flag (ef ) 18 data out (q) 18 36 first load (fl ) write expansion in (wxi ) read expansion in (rxi ) 7c4275v 7c4285v 7c4255v 7c4265v 7c4275v 7c4285v [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 9 of 24 figure 3. block diagram of 8 k/16 k/32 k/64 k 18 low voltage synchronous fifo memory with programmable flags in depth expansion configuration 4275v?25 write clock (wclk) write enable (wen ) reset (rs ) load (ld ) ff paf paf ff ef pae pae ef wxi rxi first load (fl ) read clock (rclk) read enable (ren ) output enable (oe ) wxo rxo paf ff ef pae wxi rxi wxo rxo v cc fl paf ff ef pae wxi rxi wxo rxo 7c4255v 7c4265v v cc fl data in (d) data out (q) 7c4275v 7c4285v 7c4255v 7c4265v 7c4275v 7c4285v 7c4255v 7c4265v 7c4275v 7c4285v [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 10 of 24 maximum ratings exceeding maximum ratings [4] may impair the useful life of the device. these user guidelines are not tested. storage temperature .............................. ?65 c to +150 c ambient temperature with power applied ......................................... ?55 c to +125 c supply voltage to ground potential..... ?0.5 v to v cc + 0.5 v dc voltage applied to outputs in high z state ..................................... ?0.5 v to v cc + 0.5 v dc input voltage ????????????????????????????????????? ? 0.5 v to v cc + 0.5 v output current into outputs (low)............................. 20 ma static discharge voltage.......................................... > 2001 v (per mil?std?883, method 3015) latch-up current ....... .............. ........... ............ ........ > 200 ma operating range range ambienttemperature v cc [5] commercial 0 c to +70 c 3.3 v 300 mv industrial [6] ?40 c to +85 c 3.3 v 300 mv electrical characteristics over the operating range [7] parameter description test conditions 7c4255/85v-10 7c4255/65/75/85v-15 unit min max min max v oh output high voltage v cc = min, i oh = ?1.0 ma v cc = 3.0 v. i oh = ?2.0 ma 2.4 2.4 v v ol output low voltage v cc = min, i ol = 4.0 ma v cc = 3.0 v, i ol = 8.0 ma 0.4 0.4 v v ih [8] input high voltage 2.0 v cc 2.0 v cc v v il [8] input low voltage ?0.5 0.8 ?0.5 0.8 v i ix input leakage current v cc = max ?10 +10 ?10 +10 ? a i ozl i ozh output off, high z current oe > v ih , v ss < v o < v cc ?10 +10 ?10 +10 ? a i cc1 [9] active power supply current commercial 30 30 ma industrial 35 ma i sb [10] average standby current commercial 4 4 ma industrial 4 ma capacitance parameter [11] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 5 pf c out output capacitance 7 pf notes 4. the voltage on any input or io pin cannot exceed the power pin during power up. 5. v cc range for commercial ?10 ns is 3.3 v 150 mv. 6. t a is the ?instant on? case temperature. 7. see the last page of this specification for group a subgroup testing information. 8. the v ih and v il specifications apply for all inputs except wxi , rxi . the wxi , rxi pin is not a ttl input. it is connected to either rxo , wxo of the previous device or v ss . 9. input signals switch from 0 v to 3 v with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 mhz, whil e data inputs switch at 10 mhz. outputs are unloaded. 10. all inputs = v cc ? 0.2 v, except rclk and wclk (which are at frequency = 0 mhz), and fl /rt which is at v ss . all outputs are unloaded. 11. tested initially and after any design c hanges that may affect these parameters. [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 11 of 24 figure 4. ac test loads and waveforms (?15) [12, 13] 3.0 v 3.3 v output r1 = 330 ? r2 = 510 ? c l including jig and scope gnd 90% 10% 90% 10% ? 3ns ? 3 ns output 2.0 v equivalent to: th venin equivalent 4275v?4 200 ? all input pulses 4287v?5 figure 5. ac test loads and waveforms (?10) 3.0 v gnd 90% 10% 90% 10% ? 3ns ? 3 ns all input pulses 4275v?6 i/o 50 ? v cc /2 z0 = 50 ?? 4275v?7 notes 12. c l = 30 pf for all ac parameters except for t ohz . 13. c l = 5 pf for t ohz . [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 12 of 24 switching characteristics over the operating range parameter description 7c4255/85v-10 7c4255/65/75/85v-15 unit min max min max t s clock cycle frequency 100 66.7 mhz t a data access time 2 8 2 10 ns t clk clock cycle time 10 15 ns t clkh clock high time 4.5 6 ns t clkl clock low time 4.5 6 ns t ds data setup time 3.5 4 ns t dh data hold time 0 0 ns t ens enable setup time 3.5 4 ns t enh enable hold time 0 0 ns t rs reset pulse width [14] 10 15 ns t rsr reset recovery time 8 10 ns t rsf reset to flag and output time 10 15 ns t prt retransmit pulse width 60 60 ns t rtr retransmit recovery time 90 90 ns t olz output enable to output in low z [15] 00ns t oe output enable to output valid 3 7 3 10 ns t ohz output enable to output in high z [15] 37 3 8ns t wff write clock to full flag 8 10 ns t ref read clock to empty flag 8 10 ns t pafasynch clock to programmable almost full flag [16] (asynchronous mode, v cc /smode tied to v cc ) 15 16 ns t pafsynch clock to programmable almost full flag (synchronous mode, v cc /smode tied to v ss ) 810ns t paeasynch clock to programmable almost empty flag [16] (asynchronous mode, v cc /smode tied to v cc ) 15 16 ns t paesynch clock to programmable almost full flag (synchronous mode, v cc /smode tied to v ss ) 810ns t hf clock to half full flag 12 16 ns t xo clock to expansion out 6 10 ns t xi expansion in pulse width 4.5 6.5 ns t xis expansion in setup time 4 5 ns t skew1 skew time between read clock and write clock for full flag 5 6 ns t skew2 skew time between read clock and write clock for empty flag 5 6 ns t skew3 skew time between read clock and write clock for programmable almost empty and programmable almost full flags (synchronous mode only) 10 15 ns notes 14. pulse widths less than minimum values are not allowed. 15. values guaranteed by design, not currently tested. 16. t pafasynch , t paeasynch , after program register write are valid until 5 ns + t paf(e) . [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 13 of 24 switching waveforms figure 6. write cycle timing figure 7. read cycle timing t clkh t clkl no operation t ds t skew1 t ens wen t clk t dh t wff t wff t enh wclk d 0 ?d 17 ff ren rclk [17] t clkh t clkl no operation t skew2 wen t clk t ohz t ref t ref rclk q 0 ?q 17 ef ren wclk oe t oe t ens t olz t a t enh valid data [18] notes 17. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff goes high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. 18. t skew2 is the minimum time between a rising wclk edge and a rising rcl k edge to guarantee that ef goes high during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ef may not change state until the next rclk rising edge. [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 14 of 24 figure 8. reset timing [19] figure 9. first data word latency after reset with simultaneous read and write switching waveforms (continued) t rs t rsr q 0? q 17 rs t rsf t rsf t rsf oe =1 oe =0 ren ,wen, ld ef ,pae ff ,paf , hf [20] notes 19. the clocks (rclk, wclk) can be free-running during reset. 20. after reset, the outputs are low if oe = 0 and three-state if oe = 1. 21. when t skew2 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew2 < minimum specification, t frl (maximum) = either 2 t clk + t skew2 or t clk + t skew2 . the latency timing applies only at the empty boundary (ef = low). 22. the first word is always available the cycle after ef goes high. d 0 (firstvalid write) t skew2 wen wclk q 0 ?q 17 ef ren oe t oe t ens t olz t ds rclk t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 d 0 ?d 17 t a [21] [22] [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 15 of 24 figure 10. empty flag timing figure 11. full flag timing switching waveforms (continued) d1 d0 t ens t skew2 wen wclk q 0 ?q 17 ef ren oe t ds t enh rclk t ref t a t frl d 0 ?d 17 d0 t skew2 t frl t ref t ds t ens t enh t ref [23] [23] next data read data write no write data in output register ff wclk q 0 ?q 17 ren oe rclk t a d 0 ?d 17 data read t skew1 t ds t ens t enh wen t wff t a t skew1 t ens t enh t wff data write no write t wff low [24] [24] notes 23. when t skew2 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew2 < minimum specification, t frl (maximum) = either 2 t clk + t skew2 or t clk + t skew2 . the latency timing applies only at the empty boundary (ef = low). 24. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff goes high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 16 of 24 figure 12. half full timing figure 13. programmable almost empty flag timing switching waveforms (continued) t enh wen wclk hf ren rclk t clkh t hf t ens half full + 1 or more t clkl t ens half full or less half full or less t hf t enh wen wclk pae ren rclk t clkh t pae t ens n + 1 words in fifo t clkl t ens t pae n words in fifo [25] note 25. pae is offset = n. number of data words into fifo already = n. [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 17 of 24 figure 14. programmable almost empty flag timing (applies only in smode (smode is low)) figure 15. programmable almost full flag timing switching waveforms (continued) note t enh wclk pae rclk t clkh t ens t clkl t ens t pae synch n+ 1 words in fifo t enh t ens t pae synch ren wen t skew3 note [27] 26 28 notes 26. paf offset = m. number of data words written into fifo already = 8192 ?? (m + 1) for the cy7c4255v, 16384 ?? (m + 1) for the cy7c4265v, 32768 ? (m + 1) for the cy7c4275v, and 65536 ?? (m + 1) for the cy7c4285v. 27. t skew3 is the minimum time between a rising wclk and a rising rclk edge for pae to change state during that clock cycle. if the time between the edge of wclk and the rising rclk is less than tskew3, then pae may not change state until the next rclk. 28. if a read is performed on this rising edge of the read clock, there are empty + (n ? 1) words in the fifo when pae goes low. 29. paf is offset = m. 30. 8192 ?? m words in cy7c4255v, 16384 ?? m words in cy7c4265v, 32768 ??? m words in cy7c4275v, and 65536 ?? m words in cy7c4285v. 31. 8192 ?? (m + 1) words in cy7c4255v, 16384 ?? (m + 1) words in cy7c4265v, 32768 ?? (m + 1) words in cy7c4275v, and 65536 ?? (m + 1) words in cy7c4285v. note t enh wen wclk paf ren rclk t clkh t paf t ens t clkl t ens t paf full? m words in fifo full? (m+1) words in fifo [31] [30] 26 [29] [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 18 of 24 figure 16. programmable almost full flag timing (applies only in smode (smode is low)) figure 17. write programmable registers switching waveforms (continued) note t enh wclk paf rclk t clkh t ens full? m words in fifo t clkl t ens full ? m + 1 words in fifo t enh t ens t paf ren wen t skew3 t paf synch 32 [33] [34] t enh ld wclk t clkh t ens t clkl pae offset d 0 ?d 17 wen t ens paf offset pae offset t clk d 0 ? d 11 t ds t dh notes 32. if a write is performed on this rising edge of the write clock, there are full ? (m ? 1) words of the fifo when paf goes low. 33. 8192 ?? m words in cy7c4255v, 16384 ?? m words in cy7c4265v, 32768 ??? m words in cy7c4275v, and 65536 ?? m words in cy7c4285v. 34. t skew3 is the minimum time between a rising rclk and a rising wclk edge for paf to change state during that clock cycle. if the time between the edge of rclk and the rising edge of wclk is less than t skew3 , then paf may not change state until the next wclk rising edge. [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 19 of 24 figure 18. read programmable registers figure 19. write expansion out timing figure 20. read expansion out timing figure 21. write expansion in timing switching waveforms (continued) t enh ld rclk t clkh t ens t clkl pae offset q 0 ?q 17 wen t ens paf offset pae offset t clk unknown t a wen wclk wxo t clkh t ens t xo t xo 36 35 ren wclk rxo t clkh t ens t xo t xo 35 notes 35. read from last physical location. 36. write to last physical location. wclk wxi t xi t xis [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 20 of 24 figure 22. read expansion in timing figure 23. retransmit timing [37, 38, 39] switching waveforms (continued) rclk rxi t xi t xis ren /wen fl /rt t prt t rtr ef /ff and all async flags hf /pae /paf notes 37. clocks are free-running in this case. 38. the flags may change state during retransmit as a result of the offset of the read and write pointers, but flags are valid a t t rtr . 39. for the synchronous pae and paf flags (smode), an appropriate clock cycle is necessary after t rtr to update these flags. [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 21 of 24 ordering code definitions ordering information 8 k 18 low-voltage deep sync fifo speed (ns) ordering code package diagram package type operating range 10 cy7c4255v?10asc 51-85051 64-pin thin quad flat pack (10 10 1.4 mm) commercial cy7c4255v?10asxc 64-pin thin quad flat pack (10 10 1.4 mm) (pb-free) 15 cy7c4255v?15asc 51-85051 64-pin thin quad flat pack (10 10 1.4 mm) commercial cy7c4255v?15asxc 64-pin thin quad flat pack (10 10 1.4 mm) (pb-free) cy7c4255v?15asxi 51-85051 64-pin thin quad flat pack (10 10 1.4 mm) (pb-free) industrial cy7c4255v?15asi 64-pin thin quad flat pack (10 10 1.4 mm) 16 k 18 low-voltage deep sync fifo speed (ns) ordering code package diagram package type operating range 15 cy7c4265v?15asc 51-85051 64-pin thin quad flat pack (10 10 1.4 mm) commercial 32 k 18 low-voltage deep sync fifo speed (ns) ordering code package diagram package type operating range 15 cy7c4275v?15asc 51-85051 64-pin thin quad flat pack (10 10 1.4 mm) commercial cy7c4275v?15asxc 64-pin thin quad flat pack (10 10 1.4 mm) (pb-free) 64 k 18 low-voltage deep sync fifo speed (ns) ordering code package diagram package type operating range 10 cy7c4285v?10asc 51-85051 64-pin thin quad flat pack (10 10 1.4 mm) commercial cy7c4285v?10asxc 64-pin thin quad flat pack (10 10 1.4 mm) (pb-free) 15 cy7c4285v?15asxc 51-85051 64-pin thin quad flat pack (10 10 1.4 mm) (pb-free) commercial cy7c4285v?15asc 64-pin thin quad flat pack (10 10 1.4 mm) cy7c4285v?15asi 51-85051 64-pin thin quad flat pack (10 10 1.4 mm) industrial cy7c4285v?15asxi 64-pin thin quad flat pack (10 10 1.4 mm) (pb-free) temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: as = stqfp speed: xx = 10 ns or 15 ns v = 3.3 v width: 5 = 18 depth: 2x = 25 or 26 or 27 or 28 25 = 8 kb; 26 = 16 kb; 27 = 32 kb; 28 = 64 kb fifo 7c = dual port company id: cy = cypress 4 cy 2x v - x x 7c as 5 xx [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 22 of 24 package diagram figure 24. 64-pin thin plastic quad flat pack (10 10 1.4 mm) 51-85051 *b [+] feedback
cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v document number: 38-06012 rev. *d page 23 of 24 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor fifo first-in first-out i/o input/output oe output enable ren read enable rclk read clock rt retransmit rs reset tqfp thin quad flat pack wclk write clock wen write enable symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes ms milli seconds mv milli volts mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback
document number: 38-06012 rev. *d revised december 31, 2010 page 24 of 24 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c4255v, cy7c4265v cy7c4275v, cy7c4285v ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: cy7c4255v/cy7c4265v/cy7c4275v/cy7c4285v 8 k/16 k/32 k/64 k 18 low voltage deep sync fifos document number: 38-06012 rev. ecn orig. of change submission date description of change ** 106473 szv 09/10/01 change from spec number: 38-00654 to 38-06012 *a 122264 rbi 12/26/02 power up requirements added to maximum ratings information *b 2556036 vkn/aesa 08/22/2008 updated ordering information and data sheet template. *c 2896039 rame 03/19/2010 added contents updated package diagram removed inactive parts from ordering information table updated links in sales, solutions and legal information *d 3123000 admu 12/31/2010 removed speed bin -25 added ordering code definitions . added acronyms and units of measure . updated in new template. [+] feedback

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